What is nested vector interrupt control (NVIC)?

In a microcontroller, such as those at the heart of industrial motion controllers, interrupts serve as a way to immediately divert the central processing unit from its current task to another, more important task.

An interrupt can be triggered internally from the microcontroller (MCU) or externally, by a peripheral. The interrupt alerts the central processing unit (CPU) to an occurrence such as a time-based event (a specified amount of time has elapsed or a specific time is reached, for example), a change of state, or the start or end of a process.

Interrupts can be triggered internally – from a timer, for example – or externally, from peripherals.

Another method of monitoring a timed event or change of state is referred to as “polling.” With polling, the status of a timer or state change is periodically checked. The downsides of polling are the risk of excessive latency (delay) between the actual change and its detection, the possibility of missing a change altogether, and the increased processing time and power it requires.

With polling, the CPU periodically checks for a change of state. Interrupts automatically notify the CPU when a change of state occurs, ensuring the change is not missed and its detection is not delayed.
Image credit: Renesas Electronics Corporation

When an interrupt occurs, an interrupt signal is generated, which causes the CPU to stop its current operation, save its current state, and begin the processing program — referred to as an interrupt service routine (ISR) or interrupt handler — associated with the interrupt. When the interrupt processing is complete, the CPU restores its previous state and resumes where it left off.

Nested vector interrupt control (NVIC) is a method of prioritizing interrupts, improving the MCU’s performance and reducing interrupt latency. NVIC also provides implementation schemes for handling interrupts that occur when other interrupts are being executed or when the CPU is in the process of restoring its previous state and resuming its suspended process.

The term “nested” refers to the fact that in NVIC, a number of interrupts (up to several hundred in some processors) can be defined, and each interrupt is assigned a priority, with “0” being the highest priority. In addition, the most critical interrupt can be made non-maskable, meaning it cannot be disabled (masked).

One function of NVIC is to ensure that higher priority interrupts are completed before lower-priority interrupts, even if the lower-priority interrupt is triggered first. For example, if a lower-priority interrupt is being registered* or executed and a higher-priority interrupt occurs, the CPU will stop the lower-priority interrupt and process the higher-priority one first.

* A register is a special, dedicated memory circuit within the CPU that can be written and read much more quickly than regular memory. The register is used to store information such as calculation results, CPU execution states, or other critical program information.

Similarly, a handling scheme referred to as “tail-chaining” specifies that if an interrupt is pending while the ISR for another, higher-priority another interrupt completes, the processor will immediately begin the ISR for the next interrupt, without restoring its previous state.

With tail-chaining, if an interrupt is pending as the ISR for another, higher-priority interrupt completes, the processor will immediately begin the ISR for the next interrupt, without restoring its previous state.
Image credit: Arm Limited

The term “vector” in nested vector interrupt control refers to the way in which the CPU finds the program, or ISR, to be executed when an interrupt occurs. Nested vector interrupt control uses a vector table that contains the addresses of the ISRs for each interrupt. When an interrupt is triggered, the processor gets the address from the vector table.

The prioritization and handling schemes of nested vector interrupt control reduce the latency and overhead that interrupts typically introduce and ensure low power consumption, even with high interrupt loading on the controller.

Feature image credit: Arm Limited